1 LT1949-1 1.1mhz, 1a switch pwm dc/dc converter june 2000 v in v in 3.3v sw fb LT1949-1 l1 4.7 h d1 r2 28k 1% 84.5k 50pf v out 10v 175ma r1 196k 1% 3pf 1949-1 f01 c2 3.3 f ceramic c1 3.3 f ceramic v c gnd shdn shutdown c1, c2: taiyo yuden lmk325bj335md d1: mbrm120lt3 l1: sumida clq4d10-4r7 the lt ? 1949-1 is a fixed frequency step-up dc/dc con- verter with a 1a, 0.5 w internal switch. capable of gener- ating 10v at 175ma from a 3.3v input, the LT1949-1 is ideal for generating bias voltages for large screen lcd panels. constant frequency 1.1mhz operation results in a low noise output that is easy to filter and the 30v switch rating allows output voltage up to 28v using a single inductor. the high switching frequency allows the use of ceramic output capacitors. an external compensation pin gives the user flexibility in optimizing loop compensation, allowing small, low esr ceramic capacitors to be used at the output. the 8-lead msop package ensures a low profile overall solution. the LT1949-1 includes a low-battery detector that stays alive when the device goes into shutdown. quiescent current in shutdown is 50 m a, while operating current is 8ma. n 1a, 0.5 w , 30v internal switch n 1.1mhz fixed frequency operation n operates with v in as low as 1.5v n low-battery detector stays active in shutdown n low v cesat switch: 410mv at 800ma n pin-for-pin compatible with the lt1317b n uses ceramic capacitors n small 8-lead msop package n lcd bias supplies n gps receivers n battery backup n portable electronic equipment n diagnostic medical instrumentation , ltc and lt are registered trademarks of linear technology corporation. figure 1. 3.3v to 10v/175ma dc/dc converter figure 2. 3.3v to 10v converter efficiency load current (ma) 90 80 70 60 50 40 30 20 5 100 50 300 1949-1 f02 10 efficiency (%) v out = 10v 3v in 3.6v in 4.2v in features descriptio u applicatio s u typical applicatio u final electrical specifications information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
2 LT1949-1 (note 1) v in , lbo voltage ..................................................... 12v sw voltage ............................................... C 0.4v to 30v fb voltage .................................................... v in + 0.3v v c voltage ................................................................ 2v lbi voltage ............................................ 0v v lbi 1v shdn voltage ........................................................... 6v junction temperature .......................................... 125 c operating temperature range (note 2) ...C40 c to 85 c storage temperature ........................... C 65 c to 150 c lead temperature (soldering, 10sec).................. 300 c LT1949-1ems8 ltqx consult factory for industrial and military grade parts. 1 2 3 4 v c fb shdn gnd 8 7 6 5 lbo lbi v in sw top view ms8 package 8-lead plastic msop t jmax = 125 c, q ja = 120 c/w order part number ms8 part marking the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 2v, v shdn = 2v unless otherwise noted. symbol parameter conditions min typ max units i q quiescent current l 814ma v shdn = 0v l 50 80 m a v fb feedback voltage 1.22 1.24 1.26 v l 1.20 1.24 1.26 v i b fb pin bias current (note 3) l 24 150 na input voltage range l 1.7 12 v g m error amp transconductance d i = 5 m a l 140 280 480 m mhos a v error amp voltage gain 700 v/v maximum duty cycle l 80 85 % switch current limit (note 4) v in = 2.5v, duty cycle = 30% 1 1.1 1.5 a f osc switching frequency l 0.85 1.1 1.35 mhz shutdown pin current v shdn = v in l 0.015 0.1 m a v shdn = 0v l C5 C14 m a lbi threshold voltage 190 200 210 mv l 180 200 220 mv lbo output low i sink = 10 m a l 0.15 0.25 v lbo leakage current v lbi = 250mv, v lbo = 5v l 20 100 na lbi input bias current (note 5) v lbi = 150mv l 30 120 na low-battery detector gain 1m w pull-up 2000 v/v switch leakage current v sw = 5v l 0.01 3 m a switch v cesat i sw = 800ma 410 mv i sw = 500ma l 270 400 mv reference line regulation 1.8v v in 12v 0.08 %/v shdn input voltage high l 1.4 6 v shdn input voltage low l 0.4 v package/order i for atio uu w absolute axi u rati gs w ww u electrical characteristics note 3: bias current flows into fb pin. note 4: switch current limit guaranteed by design and/or correlation to static tests. duty cycle affects current limit due to ramp generator. note 5: bias current flows out of lbi pin. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the LT1949-1e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls.
3 LT1949-1 typical perfor a ce characteristics uw input voltage (v) 0 oscillator frequency (mhz) 1.3 1.2 1.1 1.0 0.9 2468 1949-1 g01 10 12 25 c ?0 c 85 c switch current limit, duty cycle = 30% oscillator frequency switch current limit duty cycle (%) 0 switch current (a) 1.3 1.2 1.1 1.0 0.9 0.8 80 1949-1 g02 20 40 60 100 temperature ( c) ?0 switch current (a) 1.3 1.2 1.1 1.0 0.9 0.8 ?5 02550 1949-1 g03 75 100 switch voltage drop (v cesat ) switch current (a) 0 switch voltage (v) 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1949-1 g04 1.0 1.2 85 c ?0 c 25 c feedback voltage temperature ( c) ?0 feedback voltage (v) 1.25 1.24 1.23 1.22 1.21 1.20 ?5 0 25 50 1949-1 g05 75 100 quiescent current, shdn = 2v temperature ( c) ?0 25 quiescent current (ma) 1949-1 g06 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 0 255075100 quiescent current, shdn = 0v fb pin bias current temperature ( c) ?0 quiescent current ( a) 60 55 50 45 40 35 30 ?5 0 25 50 1949-1 g07 75 100 temperature ( c) ?0 60 55 50 45 40 35 30 25 20 15 10 ?5 0 25 50 75 100 fb pin bias current (na) 1949-1 g08 shdn pin current shdn pin voltage (v) 0 shdn pin current ( a) 3 5 1949-1 g09 12 4 2 1 0 ? ? ? 6
4 LT1949-1 typical perfor a ce characteristics uw transient response v out 100mv/div ac coupled i l 500ma/div v in = 3.3v 20 m s/div 1949-1 g10 v out = 10v 40ma to 140ma load step circuit figure 1 uu u pi fu ctio s v c (pin 1): compensation pin for error amplifier. con- nect a series rc network from this pin to ground. typical values for compensation are a 30k/330pf combination when using ceramic output capacitors. minimize trace area at v c . fb (pin 2): feedback pin. reference voltage is 1.24v. connect resistor divider tap here. minimize trace area at fb. set v out according to: v out = 1.24v(1 + r1/r2). shdn (pin 3): shutdown. pull this pin low for shutdown mode (only the low-battery detector remains active). leave this pin floating or tie to a voltage between 1.4v and 6v to enable the device. shdn pin is logic level and need only meet the logic specification (1.4v for high, 0.4v for low). gnd (pin 4): ground. connect directly to local ground plane. sw (pin 5): switch pin. connect inductor/diode here. minimize trace area at this pin to keep emi down. v in (pin 6): supply pin. must be bypassed close to the pin. lbi (pin 7): low-battery detector input. 200mv refer- ence. voltage on lbi must stay between ground and 700mv. low-battery detector remains active in shutdown mode. lbo (pin 8): low-battery detector output. open collec- tor, can sink 10 m a. a 1m w pull-up is recommended.
5 LT1949-1 block diagra w + + + + + + + s ramp generator 1.24v reference r bias v c g m fb enable 200mv a = 2 ff a1 comparator a2 comparator error amplifier a4 0.06 w driver sw gnd 1949-1 bd q3 q s 1.1mhz oscillator 5 lbo lbi shdn shutdown 3 7 1 4 r1 (external) v out 8 r2 (external) fb 2 figure 3. LT1949-1 block diagram the LT1949-1 is a current mode, fixed frequency step-up dc/dc converter with an internal 1a npn power transis- tor. operation can best be understood by referring to the block diagram. at the beginning of each oscillator cycle, the flip-flop is set and the switch is turned on. current in the switch ramps up until the voltage at a2s positive input reaches the v c pin voltage, causing a2s output to change state and the switch to be turned off. the signal at a2s positive input is a summation of a signal representing switch current and a ramp generator (introduced to avoid subharmonic oscil- lations at duty factors greater than 50%). if the load increases, v out (and fb) will drop slightly and the error amplifier will drive v c to a higher voltage, causing current in the switch to increase. in this way, the error amplifier drives the v c pin to the voltage necessary to satisfy the load. frequency compensation is provided by an external series rc network connected between the v c pin and ground. layout hints the LT1949-1 switches current at high speed, mandating careful attention to layout for proper performance. you will not get advertised performance with careless layouts. figure 4 shows recommended component placement for a boost (step-up) converter. follow this closely in your pc layout. note the direct path of the switching loops. input capacitor c1 must be placed close (< 5mm) to the ic package. as little as 10mm of wire or pc trace from c in to v in will cause problems such as inability to regulate or oscillation. the ground terminal of output capacitor c2 should tie close to pin 4 of the LT1949-1. doing this reduces di/dt in the ground copper which keeps high frequency spikes to a minimum. the dc/dc converter ground should tie to the pc board ground plane at one place only, to avoid intro- ducing di/dt in the ground plane. operatio u
6 LT1949-1 figure 4. recommended component placement for boost converter. note direct high current paths using wide pc traces. minimize trace area at pin 1 (v c ) and pin 2 (fb). use multiple vias to tie pin 4 copper to ground plane. use vias at one location only to avoid introducing switching currents into the ground plane operatio u low-battery detector the LT1949-1s low-battery detector is a simple pnp input gain stage with an open collector npn output. the nega- tive input of the gain stage is tied internally to a 200mv 5% reference. the positive input is the lbi pin. arrange- ment as a low-battery detector is straightforward. figure 5 details hookup. r1 and r2 need only be low enough in value so that the bias current of the lbi pin doesnt cause large errors. for r2, 49.9k is adequate. the 200mv reference can also be accessed as shown in figure 6. the low-battery detector remains active in shutdown. figure 5. setting low-battery detector trip point figure 6. accessing 200mv reference 1 2 8 7 3 4 6 5 l1 c2 lbo lbi LT1949-1 v out v in gnd shutdown r1 r2 multiple vias ground plane 1949-1 f04 c1 applicatio s i for atio wu uu lbo lbi to processor r1 1m r2 49.9k v in LT1949-1 1949-1 f05 3.3v gnd 200mv internal reference + r1 = v lb ?200mv 4 a v in LT1949-1 lbi lbo 200k 10 m f gnd 10k 1949-1 f06 2n3906 v ref 200mv +
7 LT1949-1 4 cell to 5v sepic converter typical applicatio u dimensions in inches (millimeters) unless otherwise noted. ms8 package 8-lead plastic msop (ltc dwg # 05-08-1660) u package descriptio msop (ms8) 1098 * dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.006" (0.152mm) per side 0.021 0.006 (0.53 0.015) 0 ?6 typ seating plane 0.007 (0.18) 0.040 0.006 (1.02 0.15) 0.012 (0.30) ref 0.006 0.004 (0.15 0.102) 0.034 0.004 (0.86 0.102) 0.0256 (0.65) bsc 12 3 4 0.193 0.006 (4.90 0.15) 8 7 6 5 0.118 0.004* (3.00 0.102) 0.118 0.004** (3.00 0.102) v in v in 4v to 9v sw fb LT1949-1 l1 10 h l2 10 h d1 40.2k 1m 330pf c2 4.7 f 16v v out 5v 250ma 1949-1 ta02 c3 10 f 6.3v c1 4.7 f 16v v c gnd shdn c1, c2: taiyo yuden emk316bj475ml c3: taiyo yuden jmk316bj106ml d1: motorola mbrm120lt3 l1, l2: sumida cr32-100kc 1m 100k 1% 33.2k 1%
8 LT1949-1 ? linear technology corporation 2000 19491i lt/tp 0600 4k ? printed in the usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com part number description comments lt1302 high output current micropower dc/dc converter 5v/600ma from 2v, 2a internal switch, 200 m a i q lt1304 2-cell micropower dc/dc converter low-battery detector active in shutdown lt1307b single cell micropower 600khz pwm dc/dc converter 3.3v at 75ma from 1 cell, msop package lt1308b 2a 600khz pwm dc/dc converter 36v switch, fixed frequency operation, so-8 and tssop packages lt1317b micropower, 600khz pwm dc/dc converter 2 cells to 3.3v at 200ma, msop package lt1377 monolithic 1mhz, 1.5a switching regulator regulates positive or negative outputs, ext synchronization lt1613 single cell 1.4mhz pwm dc/dc converter 3.3v to 5v at 200ma, sot-23 package lt1615 micropower boost converter in sot-23 i q = 20 m a, < 1 m a in shutdown, v out up to 34v lt1930 1.2mhz boost converter in sot-23 1a, 36v internal switching, v in = 2.6v to 16v lt1949 600khz, 1a switch pwm dc/dc converter 1a, 0.5 w , 30v internal switch, 8-lead msop and so packages related parts low profile triple output lcd bias generator typical applicatio u v in v in 3.3v sw fb LT1949-1 l1 4.7 h r2 40.2k r1 30.1k r3 7.5k 1949-1 ta02 c2 4.7 f c6 1 f c7 0.1 f c8 1 f c9 0.1 f c4 1 f c5 4.7 f c1 4.7 f c3 330pf d5 d1 d2 ?v 10ma 8v 200ma 23v 5ma d6 v c gnd shdn shutdown c1, c2, c5: taiyo yuden lmk325bj475mf c4, c6, c8: taiyo yuden emk316bj105mf d1 to d6: bat-54s, dual diode d7: mbrm120lt3 l1: sumida clq4d10-4r7 d3 d4
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